1. Field of the Invention
The present invention relates to a thermally enhanced electronic package, and more particularly, to an electronic package with high thermal dissipation capability.
2. Description of the Related Art
Continuous demand for improved performance of semiconductor products results in higher operating frequencies and greater power consumption. Therefore, electrical packages having high thermal conductivity capable of effective heat dissipation to reduce interconnect junction temperatures are needed for semiconductor products. One such electrical package is a type of semiconductor device called a liquid crystal display (LCD) driver. In addition, heat management solutions are also needed for high power packages using substrates as chip carriers.
A typical high power package known as a fine pitch ball grid array (FBGA) is illustrated in FIG. 1. The FBGA package 10 comprises a chip 11 and a substrate 14. The substrate 14 can be a rigid or flexible printed circuit board. The chip 11 is mounted on the substrate 14 by a die attaching material 15 such as an adhesive film. Metal wires 13 are connected to the substrate 14 from the active surface of the chip 11. Encapsulants 12 cover the chip 11, the substrate 14 and the metal wires 13 to protect the chip 11 and the metal wires 13 from damage. Solder balls 16 are disposed on the substrate 14, and act as the I/O terminals of the FBGA package 10. With the circuits densely arranged on a limited area of the chip 11, more heat is generated, and the FBGA package 10 suffers from insufficient thermal dissipation. The encapsulants 12 include epoxy resin, which has poor thermal conductivity, causing the heat to accumulate in the FBGA package 10. In general, the insulating layers of the substrate 14 are polymers which also have poor thermal conductivity, so the accumulated heat is not easily dissipated from the insulating layers to the outside of the FBGA package 10.
A new generation of three-dimensional integrated circuits and components is emerging. The arrangement involving stacking of two-dimensional chips by sandwiching two or more ICs using a fabrication process required a solution to create vertical connections between the layers. IBM solved this problem by developing “through silicon vias” (TSVs) which are vertical connections etched through the silicon wafer and filled with metal. The approach of using TSVs to create 3D connections allows the addition of a greater number of pathways between 2D layers.
FIG. 2 shows a three-dimensional IC package using TSVs. The 3D IC package 20 comprises a plurality of IC chips (211, 212), TSVs (231, 232), and a substrate 24. The TSVs 231, 232 are formed through the IC chips (211, 212) with a plurality of micro bumps (or soft metal caps) 233 formed respectively on the surfaces of TSVs 231, 232. The plurality of micro bumps 233 are used for electrically connecting IC chips (211, 212) and connecting the substrate 24 to adjacent TSVs 231, 232. Adhesives 25 attach the chips (211, 212) together and mount them onto the substrate 24. An encapsulant 22 covers the chips (211, 212) and the substrate 24. Several passive IC chips 241 are embedded into the substrate 24, and terminals or electrodes 242 are disposed on the lower surface of the substrate 24.
In the conventional 3D IC package 20, many chips (211, 212) are put into a package body. Each chip generates heat, which is accumulated in the package body. The accumulated heat cannot be effectively dissipated to the outside through the encapsulant 22 or the substrate 24. Therefore, to remedy the conventional drawbacks, novel materials and methods are needed to improve the thermal performance of the package.